1. Field of the Invention
The present invention relates to semiconductor devices, particularly to soft error reduction in semiconductor devices.
2. Description of the Related Art
Consumer electronic appliances operating on a battery often require reduction in the power consumption of a microcomputer incorporated therein.
As disclosed in Japanese Laid Open Patent Application No. Jp-A Heisei 5-108193, one approach for reducing power consumption of a microcomputer is to reduce the power supply voltage and/or the clock signal frequency, when high speed operation is not required.
FIG. 1 illustrates a typical structure of a microcomputer which adopts the above-described approach. A microcomputer 100 is provided with a voltage control circuit 10, a peripheral circuit 20, a CPU (Central Processing Unit) 30, a RAM (Random Access Memory) 40, a frequency divider circuit 50 and a register 60. The voltage control circuit 10 receives an external power supply voltage VDD0 from a power supply terminal. The peripheral circuit 20, the CPU 30, the RAM 40, the frequency divider circuit 50 and the register 60 are connected to the voltage control circuit 10. The CPU 30 is connected to the frequency divider circuit 50 and the register 60. The frequency divider circuit 50 is connected to a clock terminal to which an external clock CLK0 is supplied.
The microcomputer 100 in FIG. 1 operates as follows: The voltage control circuit 10 feeds an internal power supply voltage to the peripheral circuit 20, the CPU 30, and the RAM 40. The voltage control circuit 10 controls the voltage level of the internal power supply voltage. The internal power supply voltage may have a voltage level identical to that of the external power supply voltage VDD0, or lower than that of the external power supply voltage VDD0. The frequency divider circuit 50 is designed to control the frequency of an internal clock signal fed to the CPU 30. In a certain operation, the frequency of the internal clock signal may be identical to that of the external clock signal CLK0, while the internal clock signal may be generated by frequency-dividing of the external clock CLK0. The operations of the voltage control circuit 10 and the frequency divider circuit 50 are controlled on a value set to the register 60 by the CPU 30. For example, when the value set to the register 60 is “0”, the voltage control circuit 10 controls the internal power supply voltage to the same level as the external power source voltage VDD0, and the frequency divider circuit 50 controls the frequency of the internal clock signal to the same frequency as the external clock signal CLK0. When the value of the register 60 is “1”, on the other hand, the voltage control circuit 10 generates the internal power supply voltage through stepping down the external power source voltage VDD0, and the frequency divider circuit 50 generates the internal clock signal through frequency-dividing of the external clock signal CLK0. As a result, the operation voltage is controlled in accordance with the operation frequency, and the power consumption is reduced.
One issue of the microcomputer 100 shown in FIG. 1 is an increased soft error rate caused by the reduction of the operation voltage. The “soft error” is a phenomenon that electric charges are generated within a memory cell by an incoming radiation of a cosmic ray, such as, an alpha ray and a neutron ray, and data stored in the memory cell is undesirably destroyed by the generated electric charges. The soft error rate depends on a RAM capacity and a RAM operation voltage. In accordance with an increase in the capacity of the RAM (or the area of the RAM), the possibility also increases that the RAM suffers from a soft error. The reduction in the RAM operation voltage also increases the possibility in which the RAM suffers from a soft error, because the operation voltage reduction is accompanied by reduction in the charges stored in memory cells.